Instrument features

Software &
system features

Shared software for all devices

FPGA hardware triggering from edges to protocol frames and multi-step sequences, 137 protocol decoders, digital pattern generation and capture analysis. Software, firmware and gateware are open source.

Trigger types
7 + 1Signal trigger types plus the external trigger input; 1.43 ns to 24 s18Protocols with FPGA hardware triggering4Trigger steps per sequence, with independent conditions and timeouts137Protocol decoders, including I²C, SPI, UART, CAN and USB PD

01 / Hardware triggering

Hardware trigger types

Every trigger is evaluated in the FPGA at 700 MS/s, before capture decimation, so the decision does not depend on the host. Basic triggers cover edges, logic patterns and the external input. Advanced triggers add time qualification, two-input timing and protocol frames; sequences chain up to four steps.

Basic

Edge, logic pattern and the MCX external input. The usual starting points, with the same 1.43 ns resolution as every other type.

EDGE · PATTERN · EXTERNAL

Advanced timing

Pulse width, timeout, Nth edge, A-to-B delay and setup/hold violations. Time conditions take below, above, inside or outside limits; holdoff suppresses re-triggering for up to 24 s.

PULSE · TIMEOUT · NTH · DELAY · SETUP/HOLD

Protocol

Frame, field and error conditions decoded in the FPGA: select a protocol, then match the frame, field or error that matters to your capture.

CAN · CAN FD · UART · LIN · FLEXRAY · USB PD · SENT · T1S

Sequence

Up to four signal steps in a row; one step arms the next and the last triggers. Time-outs restart the sequence.

STEP 1 → 2 → 3 → 4

Basic

Advanced timing

Protocol

Sequence

LA16 / FPGA TRIGGER · ADVANCED TIMING

Pulse-width trigger

Trigger on high or low pulses with widths below, above, inside or outside the selected time limits.

PRE-TRIGGER HISTORYAFTER TRIGGER
Illustrative timing diagram · Not to scale

D0 · High pulse < 20 ns

The trigger fires at the end of the qualifying pulse.

Signal triggers evaluated in the FPGA at 700 MS/s; limits 1.43 ns to 24 s.
TriggerClassSettingsFires
EdgeBasicInput; rising, falling or either edgeAt the edge
PatternBasicH / L / don’t care per input; qualifier: enters, exits, lasts (time condition), holds longer than tWhere the pattern starts, ends or meets its time condition
External inputBasicMCX trigger input; rising, falling or either edge; independent thresholdAt the external edge; routes to capture or generator start
Pulse widthAdvancedInput; high or low pulse; width < t, > t, inside or outside t1..t2At the edge that ends a qualifying pulse
TimeoutAdvancedInput; level after the edge (high, low, either); time tt after the edge if the line still holds the level
Nth edgeAdvancedInput; edge; idle time; N = 1..65535At the Nth edge of a burst that follows the idle time
A → B delayAdvancedInput A + edge; input B + edge; condition on the A-to-B timeAt the B edge
Setup / holdAdvancedData input; clock input + edge; setup time, hold time; check either or bothAt the clock edge (setup) or the data edge (hold) that violates the window
HoldoffAdvanced0–24 s in 5.7 ns steps; applies to every typeSuppresses re-triggering until the holdoff has elapsed
Each protocol engine is a dedicated LA16 FPGA image selected by the driver. The trigger marker is the decision point, which can be the end of the frame; keep enough pre-trigger history.
ProtocolTrigger conditions
CANValid frame filtered by identifier, frame type and masked data bytes; CRC, missing ACK, stuff and form errors; active error flag.
CAN FDAs CAN, with the FD CRC lengths, fixed-stuff and stuff-count errors and the FD form bits.
UART / USARTA value or a sequence of up to 16 characters; parity and framing errors, break, idle timeout.
LINBreak, header, identifier with mask, identifier plus data bytes; parity, sync, checksum and framing errors; wake-up.
FlexRayValid frame with filters; frame start; header fields before the frame ends; header-CRC, frame-CRC and coding errors; CAS/MTS symbol; wake-up.
USB Power DeliveryPacket with filters; ordered sets (SOP, Hard Reset, Cable Reset); fields of a running packet; CRC, EOP, 4B5B code and framing errors.
SENTFast-channel frame with status/data filter; slow-channel message with ID/data filter; CRC, calibration, nibble and pause errors; Nth occurrence.
10BASE-T1SFrame with filters and length limits; frame start; fields of a running frame; FCS, end-delimiter, coding and length errors.
I2C, I3C, MDIO, SPI, USB low/full speed, encoderAddress, data and error conditions per protocol specification.
JTAG, Modbus RTU, 1-WireInstruction, register and error conditions per protocol specification.

Trigger sequences

Up to four signal trigger steps in a row, each with its own inputs and settings. One step arms the next; the last step triggers the capture.

  • Any of the signal trigger types can be a step, with its own input lines.
  • A step’s deciding sample must follow the previous step’s by at least 80 ns.
  • An optional time-out per step restarts the sequence from step 1; restarts are counted and reported.
  • The trigger marker, holdoff and pre-trigger allocation belong to the last step.
  • Protocol steps are not part of the main-image sequence; a single protocol trigger uses its own image.

Trigger holdoff

0–24 s between accepted triggers, in 5.7 ns steps. Forced and arm triggers are not held off.

LA16 and scope

Control Hub uses a shared trigger interface. Select the source, condition and pre-trigger history for the connected instrument.

Decision point

Protocol triggers decide at the end of the frame or field they match. Set enough pre-trigger history to keep the start of the transaction in the record.

LA16 trigger timing

The signal engine evaluates inputs at 700 MS/s before capture decimation. This is the trigger-engine rate; input frontend bandwidth is specified separately. Delay and setup/hold modes check the first relevant edges in each four-sample cycle. Timeout and burst-idle settings require at least four samples. Multi-line patterns can be affected by input skew of up to about 3 ns between lines.

Protocol modes use dedicated FPGA images selected by the driver; these are not all simultaneous trigger engines.

02 / Protocol analysis

Protocol decoding

Decoded addresses, data and errors are displayed alongside the waveform, on every device, with no separate protocol licences. Search the matrix for a protocol or a device-specific decoder.

137protocol
decoders

Decode I²C, SPI, UART, CAN, USB PD, Modbus and more. Search below for the protocols you use.

137 protocols shown

Decoder source: Native decoders are implemented in Control Hub; Library decoders come from the open-source libsigrokdecode library. Pattern generation and hardware triggering refer to the LA16.
ProtocolInterfaceDecode supportedDecoder sourcePattern generation supportedHardware triggering supported
1-WireInputs: 1Digital / analogYesNativeYesYes
10BASE-T1L (PAM3)Inputs: the pair's two legsAnalogYesNativeNoNo
10BASE-T1SInputs: positive, negativeDigital / analogYesNativeYesYes
24xx EEPROM24xx series I²C EEPROM commandsDigital / analogYesLibraryNoNo
93xx EEPROM93xx series Microwire EEPROM commandsDigital / analogYesLibraryNoNo
100BASE-T1 (PAM3)Inputs: the pair's two legsAnalogYesNativeNoNo
AC'97Audio Codec ’97 AC-Link between controller and codecDigital / analogYesLibraryNoNo
AD5626Analog Devices AD5626 12-bit DAC (SPI)Digital / analogYesLibraryNoNo
AD7910 / AD7920Analog Devices AD79x0 SPI ADCDigital / analogYesLibraryNoNo
ADE77xxAnalog Devices ADE77xx energy-metering IC (SPI)Digital / analogYesLibraryNoNo
ADF4350 / ADF4351Analog Devices ADF435x wideband synthesizer registersDigital / analogYesLibraryNoNo
ADNS-5020Avago ADNS-5020 optical mouse sensorDigital / analogYesLibraryNoNo
ADXL345Analog Devices ADXL345 three-axis accelerometerDigital / analogYesLibraryNoNo
AM230x / DHTxxAosong AM230x and DHTxx humidity and temperature sensorsDigital / analogYesLibraryNoNo
Amulet ASCIIAmulet LCD module ASCII command protocolDigital / analogYesLibraryNoNo
ARM ETMv3ARM Embedded Trace Macrocell v3 instruction traceDigital / analogYesLibraryNoNo
ARM ITMARM Instrumentation Trace MacrocellDigital / analogYesLibraryNoNo
ARM TPIUARM Trace Port Interface Unit framingDigital / analogYesLibraryNoNo
ATSHA204AMicrochip ATSHA204A crypto authentication (I²C)Digital / analogYesLibraryNoNo
AUDRenesas / Hitachi Advanced User Debugger traceDigital / analogYesLibraryNoNo
AVR ISPAVR in-system programming commands (SPI)Digital / analogYesLibraryNoNo
AVR PDIAVR Program and Debug InterfaceDigital / analogYesLibraryNoNo
BiSS-CInputs: MA, SLODigital / analogYesNativeYesNo
Bit-rate guessBit-rate / baud-rate estimationDigital / analogYesLibraryNoNo
CANInputs: CAN (or CAN_H / CAN_L analog)Digital / analogYesNativeYesYes
CAN FDInputs: CANDigital / analogYesNativeYesYes
CC1101TI CC1101 sub-1 GHz transceiver registers (SPI)Digital / analogYesLibraryNoNo
CFP100 Gbit/s CFP optical module management (MDIO)Digital / analogYesLibraryNoNo
cJTAGCompact JTAG, IEEE 1149.7Digital / analogYesLibraryNoNo
CounterEdge and pulse counterDigital / analogYesLibraryNoNo
DALIInputs: 1Digital / analogYesNativeYesNo
DCF77DCF77 time-signal framesDigital / analogYesLibraryNoNo
Digital caliperDigital caliper serial measurement outputDigital / analogYesLibraryNoNo
DMX512Inputs: 1Digital / analogYesNativeYesNo
DS28EA00Maxim DS28EA00 1-Wire digital thermometerDigital / analogYesLibraryNoNo
DS1307Dallas DS1307 real-time clock (I²C)Digital / analogYesLibraryNoNo
DS2408Maxim DS2408 1-Wire eight-channel switchDigital / analogYesLibraryNoNo
DS2432 / DS2433Maxim DS243x 1-Wire EEPROMDigital / analogYesLibraryNoNo
DSIDigital Serial Interface lighting controlDigital / analogYesLibraryNoNo
EDIDExtended Display Identification Data (I²C)Digital / analogYesLibraryNoNo
EM4100EM4100 125 kHz RFID tag dataDigital / analogYesLibraryNoNo
EM4305EM4305 125 kHz RFID commandsDigital / analogYesLibraryNoNo
ENC28J60Microchip ENC28J60 Ethernet controller (SPI)Digital / analogYesLibraryNoNo
FlexRayInputs: 1Digital / analogYesNativeYesYes
Gray codeGray-code and rotary encoderDigital / analogYesLibraryNoNo
HDCPHDCP over HDMI (I²C)Digital / analogYesLibraryNoNo
HDMI-CECInputs: 1Digital / analogYesNativeYesNo
I2CInputs: SCL, SDADigital / analogYesNativeYesYes
I2C demuxI²C demultiplexer by slave addressDigital / analogYesLibraryNoNo
I2C filterI²C filter by slave addressDigital / analogYesLibraryNoNo
I2SInputs: SCK, WS, SDDigital / analogYesNativeYesNo
I3C (SDR, HDR-DDR)Inputs: SCL, SDADigital / analogYesNativeYesYes
IEEE-488 / GPIBIEEE-488 (GPIB, HP-IB) busDigital / analogYesLibraryNoNo
IR remote (IRMP)Infrared remote, IRMP multi-protocolDigital / analogYesLibraryNoNo
IR remote (NEC, extended NEC, RC-5, RC-5X)Inputs: 1Digital / analogYesNativeYesNo
IR remote (RC-6)Infrared remote, RC-6Digital / analogYesLibraryNoNo
IR remote (SIRC)Infrared remote, Sony SIRCDigital / analogYesLibraryNoNo
JitterJitter between two signalsDigital / analogYesLibraryNoNo
JTAGInputs: TCK, TMS, TDI, TDO (+ TRST)Digital / analogYesNativeYesYes
LFASTNXP LFAST high-speed serial linkDigital / analogYesLibraryNoNo
LINInputs: 1Digital / analogYesNativeYesYes
LM75LM75 temperature sensor (I²C)Digital / analogYesLibraryNoNo
LPCLow Pin Count busDigital / analogYesLibraryNoNo
LTC26x7Linear Technology LTC2607 / 2617 / 2627 DACDigital / analogYesLibraryNoNo
LTC2421 / LTC2422Linear Technology LTC242x ADCDigital / analogYesLibraryNoNo
ManchesterInputs: 1Digital / analogYesNativeYesNo
Maple busSEGA Dreamcast Maple peripheral busDigital / analogYesLibraryNoNo
MAX7219 / MAX7221Maxim MAX72xx LED display driverDigital / analogYesLibraryNoNo
MCP230xxMicrochip MCP230xx I/O expander (I²C)Digital / analogYesLibraryNoNo
MCS-48Intel MCS-48 external memory accessDigital / analogYesLibraryNoNo
MDIOInputs: MDC, MDIODigital / analogYesNativeYesYes
MicrowireMicrowire three-wire serial busDigital / analogYesLibraryNoNo
MIDIInputs: 1Digital / analogYesNativeYesNo
MillerMiller encoding (ISO 14443)Digital / analogYesLibraryNoNo
MIPS EJTAGMIPS EJTAG debug over JTAGDigital / analogYesLibraryNoNo
MLX90614Melexis MLX90614 infrared thermometerDigital / analogYesLibraryNoNo
Modbus RTUInputs: 1Digital / analogYesNativeYesYes
MorseMorse codeDigital / analogYesLibraryNoNo
MRF24J40Microchip MRF24J40 IEEE 802.15.4 transceiverDigital / analogYesLibraryNoNo
MXC6225XUMEMSIC MXC6225XU accelerometerDigital / analogYesLibraryNoNo
NES gamepadNintendo NES gamepad shift registerDigital / analogYesLibraryNoNo
nRF24L01(+)Nordic nRF24L01 2.4 GHz transceiver (SPI)Digital / analogYesLibraryNoNo
nRF905Nordic nRF905 sub-1 GHz transceiver (SPI)Digital / analogYesLibraryNoNo
Numbers and stateNumbers and state from parallel dataDigital / analogYesLibraryNoNo
OOKOn-off keying demodulated dataDigital / analogYesLibraryNoNo
OOK visualisationOOK pulse visualisationDigital / analogYesLibraryNoNo
Oregon ScientificOregon Scientific weather sensors (OOK)Digital / analogYesLibraryNoNo
PAN1321Panasonic PAN1321 Bluetooth module (UART)Digital / analogYesLibraryNoNo
Parallel busInputs: clock + up to 16 data + enableDigital / analogYesNativeYesNo
PCA9571NXP PCA9571 I/O expander (I²C)Digital / analogYesLibraryNoNo
PJDLPJON data link layerDigital / analogYesLibraryNoNo
PJONPJON network protocolDigital / analogYesLibraryNoNo
PS/2Inputs: CLK, DATADigital / analogYesNativeYesNo
PWMInputs: 1Digital / analogYesNativeYesNo
QiQi wireless charging communicationDigital / analogYesLibraryNoNo
RC encoderPT2262 / HX2262 remote-control encoderDigital / analogYesLibraryNoNo
RFM12HopeRF RFM12 transceiver (SPI)Digital / analogYesLibraryNoNo
RGB LED (SPI)SPI-driven RGB LED stringsDigital / analogYesLibraryNoNo
RTC-8564Epson RTC-8564 real-time clock (I²C)Digital / analogYesLibraryNoNo
S.BUSFutaba S.BUS RC servo busDigital / analogYesLibraryNoNo
S/PDIFInputs: 1Digital / analogYesNativeYesNo
SAE J1850 VPWSAE J1850 variable pulse width (OBD-II)Digital / analogYesLibraryNoNo
SD card (native 1 / 4 bit)Inputs: CLK, CMD, DAT0..3Digital / analogYesNativeYesNo
SD card (SPI mode)SD card SPI modeDigital / analogYesLibraryNoNo
SDA2506Siemens SDA2506 EEPROMDigital / analogYesLibraryNoNo
SDQApple SDQ single-wire busDigital / analogYesLibraryNoNo
SENTInputs: 1Digital / analogYesNativeYesYes
Seven-segment displaySeven-segment display segments to digitsDigital / analogYesLibraryNoNo
Signature analysisSignature analysisDigital / analogYesLibraryNoNo
SIPISIPI serial interfaceDigital / analogYesLibraryNoNo
SLE 44xxSLE 4418 / 4428 / 4432 / 4442 memory cardsDigital / analogYesLibraryNoNo
SPIInputs: SCLK, MOSI, MISO, CSDigital / analogYesNativeYesYes
SPI NOR flash commandsInputs: SCLK, MOSI, MISO, CSDigital / analogYesNativeYesNo
SSI (32-bit)Synchronous Serial Interface, 32-bit framesDigital / analogYesLibraryNoNo
SSI encoderInputs: MA, SLODigital / analogYesNativeYesYes
ST25R39xxST ST25R39xx NFC reader (SPI)Digital / analogYesLibraryNoNo
ST7735Sitronix ST7735 TFT display controllerDigital / analogYesLibraryNoNo
Stepper motorStepper motor speed and positionDigital / analogYesLibraryNoNo
STM32 JTAGSTM32 debug over JTAGDigital / analogYesLibraryNoNo
SWDInputs: SWCLK, SWDIODigital / analogYesNativeYesNo
SWIMSTM8 single-wire interface moduleDigital / analogYesLibraryNoNo
T55xxT55xx 125 kHz RFID commandsDigital / analogYesLibraryNoNo
TCA6408ATI TCA6408A I/O expander (I²C)Digital / analogYesLibraryNoNo
TDM audioTime-division multiplexed audioDigital / analogYesLibraryNoNo
TimingTiming between edgesDigital / analogYesLibraryNoNo
TLC5620TI TLC5620 quad DACDigital / analogYesLibraryNoNo
UART / RS-232Inputs: TX, RXDigital / analogYesNativeYesYes
USART (synchronous / asynchronous)Inputs: TX, RX, CLKDigital / analogYesNativeYesYes
USB low / full speedInputs: D+, D-Digital / analogYesNativeYesYes
USB Power DeliveryInputs: CCDigital / analogYesNativeYesYes
WiegandWiegand access-control interfaceDigital / analogYesLibraryNoNo
Wii NunchukNintendo Wii Nunchuk (I²C)Digital / analogYesLibraryNoNo
WS281x LEDsInputs: DINDigital / analogYesNativeYesNo
X2444MXicor X2444M NOVRAMDigital / analogYesLibraryNoNo
XFP10 Gbit/s XFP optical module managementDigital / analogYesLibraryNoNo
XY2-100XY2-100 galvanometer scanner interfaceDigital / analogYesLibraryNoNo
Z80 busZilog Z80 bus cyclesDigital / analogYesLibraryNoNo

03 / Digital stimulus

Digital pattern generator

Create protocol traffic, edit signal timing and play it through the LA16's eight digital outputs. Capture the result with the logic analyser to check decoding and trigger conditions.

Protocol recipes and timing edits

The Patterns page includes 34 digital recipes. Arrange clips on tracks, edit recipe settings, draw edges, insert glitches and undo edits. Import and export patterns as CSV.

Eight outputs in two banks

P0–P7 are push-pull outputs in two groups of four. Hardware supports a logic-high setting of 1.65–3.3 V or 5 V per bank.

Clock, PWM and stored patterns

The vector clock is 100 MHz / N, with 10 ns timing steps. Hardware modes include static values, counters, PRBS31, per-line PWM and stored patterns with loop or one-shot playback.

Open full size ↗ (new tab)
Control Hub Patterns page showing a UART clip, editable timing track, recipe controls and device output settings.
UART recipe in the Patterns editor. Select a clip to change its settings, make an editable copy or insert a glitch.

Control Hub pattern editing, output voltage settings and SPI loopback capture.

Patterns page: 4,096 vectors

Play fits the pattern into the hardware buffer by choosing a vector clock. If the recipe does not fit at its intended rate, playback uses a slower clock. Check the applied rate for timing-sensitive protocols; the default S/PDIF recipe exceeds this buffer at its true rate.

Long patterns through the driver/API

Shared capture memory supports up to 268 million vectors, depending on the memory split. Use the driver/API for patterns larger than the Patterns page buffer.

Synchronisation and electrical interface

The analyser can trigger on pattern start. The hardware also provides a pattern-start sync pulse and an external-edge start mode through the trigger connector.

Recipes generate logic-level waveforms. A bus may require a transceiver, level conversion or another interface circuit. Playing USB PD messages does not make the generator a PD source, sink or contract negotiator. PAM3 recipes for 10BASE-T1L and 100BASE-T1 require analog outputs and are not offered on the LA16 Patterns page.

04 / Features by layer

Software, firmware, gateware and hardware

Each feature belongs to one layer. Software, firmware and gateware are open source and every software feature is included on every device; hardware files follow the platform release policy.

Control Hub

Software

Open source · all features on every device
  • Protocol decoding

    36 native decoders; 101 further protocols through the libsigrokdecode library integration.

    LA16, scope
  • Capture analysis

    Cursors, measurements, zoom and a 64-record capture history with trigger navigation.

    LA16, scope
  • Digital pattern editor

    34 protocol recipes, clip editor and per-bank voltage settings for the Patterns page.

    LA16
  • Measurement benches

    USB PD, PoE, Modbus RTU and SPI flash analyzers combining instruments and test fixtures.

    LA16 + fixtures
  • Third-party instruments

    Drivers for supported bench equipment over USB, Ethernet, RS-232 and GPIB.

    Existing equipment
  • Network API

    HTTP and WebSocket control of every widget, screenshots and a browser UI relay on one port.

    All devices
  • Desktop, browser, tablet and remote access

    One application; the shared touchscreen and remote browsers show the same session.

    All devices
  • Assistant

    Natural-language capture setup and decoding through the network API.

    All devices

Instrument controller

Firmware

Open source
  • Instrument command set

    SCPI-style commands for acquisition, every trigger type, holdoff and pattern playback; settings are validated before arming.

    LA16
  • USB-C 3.0 and gigabit Ethernet transport

    Bounded streaming buffers with counts and checksums; abort and re-arm.

    LA16
  • Host-loaded FPGA images

    The driver selects the gateware image, including the protocol trigger images.

    LA16
  • Per-device calibration

    Threshold slope and offset per input group and for the trigger input.

    LA16
  • Scope acquisition firmware

    Acquisition modes, trigger coupling and hardware settings from the device descriptor.

    Scope

FPGA

Gateware

Open source
  • Capture engine

    16 inputs into DDR sample memory with pre- and post-trigger allocation.

    LA16
  • Signal trigger engine

    Seven trigger types with holdoff, evaluated at 700 MS/s before capture decimation.

    LA16
  • Protocol trigger engines

    Frame, field and error conditions for CAN, CAN FD, serial buses, USB PD and other protocols.

    LA16
  • Trigger sequences

    Up to four signal steps in the main image; one step arms the next.

    LA16
  • External trigger input and output

    Trigger-in to capture or generator start; trigger-out and generator-start pulses on the MCX connector.

    LA16
  • Pattern playback

    4,096-vector page buffer plus long patterns streamed through the driver.

    LA16
  • Scope acquisition

    Four-channel 14-bit capture with the shared trigger interface.

    Scope

Modules and rack

Hardware

Files released per the platform policy
  • 16 capture inputs

    Four threshold groups with independent references; 200 MHz input frontend.

    LA16
  • 8 pattern outputs

    Two drive-voltage groups, 1.65–3.3 V adjustable or 5 V.

    LA16
  • MCX trigger input / output

    Independent threshold; does not consume a capture channel.

    LA16
  • USB-C 3.0 and 1G Ethernet

    Host interfaces on every module; USB-C powered.

    All modules
  • 2U module format and seven-slot rack

    Shared touchscreen and host computer as the base system.

    Platform
  • Isolated measurement sides

    Isolation barrier between measurement and host sides on the multimeter, power supply, load and SMU.

    DMM, PSU, load, SMU

System architecture

Control Hub connects over USB or Ethernet to controller firmware and FPGA capture logic. Firmware configures the FPGA, which controls acquisition and exchanges signals with measurement hardware. Supported third-party instruments connect over USB, Ethernet, RS-232 or GPIB.
Logical architecture for FPGA-based instruments such as the LA and scope. Interfaces and hardware functions vary by product.

05 / Open source & access

Open source and software access

All software features are available across all devices. Advanced analysis, protocol decoding and every trigger type the hardware supports are part of the system, with no paid software tiers or feature keys.

Read the source release policy ↗

Software, firmware and gateware

Control Hub, controller firmware and FPGA gateware are open source.

Device compatibility

Use shared analysis wherever the captured data is compatible. Device-specific bandwidth, channel count and hardware trigger support are listed separately.

Source and licences

Source packages include their licence terms. The platform policy describes access to software and instrument hardware files.

Existing equipment

Control Hub connects to supported third-party instruments as well as Modular Bench hardware. Use the equipment already in your lab through the same application.

Supported devices

AI features

Set up decoders with a local model, describe custom sequences with Vibe Trigger, and control the bench through the AI assistant or an MCP-compatible client. Bring your own model and API key for the assistant.

Explore AI features

Control Hub

Instrument software

Four-channel waveform display with SPI decoding, packet results and channel controls.

APPLICATION SCREENSHOTS
Theme
View
Open full size (opens in a new tab)
Control Hub oscilloscope in the light theme, showing four waveforms, SPI decode annotations and a packet table.
Four-channel capture with SPI packet decoding.LIGHT / CAPTURE

Protocol support matrix