modularbenchTEST & MEASUREMENT

Instrument module · MB-LA16

Logic Analyser

16 digital inputs, eight pattern outputs and a dedicated external trigger. Grouped logic thresholds, USB 3 and Gigabit Ethernet in the 2U module format.

To be announcedPricing

SKU MB-LA16

Specifications Architecture Configure a lab with this module
Logic Analyser enclosure in a three-quarter bench view, with black housing and blue handles
Front elevation of the Logic Analyser, showing four stacked probe connectors and blue handles

1 / 2Bench view

Software · Firmware · Gateware

Triggering and analysis

The LA evaluates signal and protocol triggers in the FPGA. Control Hub combines capture analysis, decoded messages and timing measurements.

View trigger types
01 / CAPTURE

Basic & advanced triggers

Edges, pulse widths, timing conditions and protocol events.

02 / DECODE

137 protocol decoders

I²C, SPI, UART, CAN, USB PD and more.

03 / GENERATE

Digital pattern generator

Eight LA outputs, 34 digital recipes and a timing editor.

SOFTWARE ACCESS

No paid feature unlocks

All software features are included across devices.

Block diagram

Architecture

Sixteen digital inputs and eight pattern outputs share one FPGA acquisition engine with DDR sample memory. The trigger input/output connects to the FPGA separately from the MCU host interfaces. Trigger input does not consume a capture channel. The MCU presents the module over USB-C 3.0 and gigabit Ethernet.

BLOCK-LEVEL · NOT A SCHEMATIC
Logic analyser block diagram: 16 capture inputs, eight pattern outputs, FPGA and DDR memory, MCU with USB-C 3.0 and gigabit Ethernet, and a separate trigger input/output below the host connectors connected to the FPGA

Specifications

Input ranges, acquisition modes and operating conditions.

Digital inputs
16Four threshold groups
Pattern outputs
8Two drive-voltage groups
Normal input range
0–5 VLogic signals
Input frontend
200 MHzInput bandwidth

Digital inputs

16 capture inputs with an independent threshold setting for each group of four.

ParameterSpecificationConditions
Input channels16Hardware definition
Threshold groups4 × 4 channels: 0–3, 4–7, 8–11, 12–15Independent group settings
Normal input range0–5 V logicConnector voltage relative to ground
Logic families1.2 / 1.8 / 2.5 / 3.3 V CMOS; 5 V TTL and CMOSSix defined threshold modes
Input frontend frequency200 MHzInput frontend; sample rate is separate
DC input resistance22.68 kΩ nominal12.68 kΩ / 10.0 kΩ divider
Input current at 5 VApproximately 220 µACalculated DC loading before leakage
Threshold calibrationSlope and offset per four-channel groupPer-group calibration

Detailed specifications

Pattern outputs

10 parameters

Eight dedicated outputs, separate from the capture inputs. Each four-channel group has its own drive-voltage setting.

ParameterSpecificationConditions
Output channels8Two groups of four
Adjustable logic level1.65–3.3 V per groupIndependent voltage setting for each bank
Nominal 5 V modeUSB-derived 5 V / 5 V CMOSFollows source, cable and load; not precision regulated
Output frequency50 MHzPattern output frequency
Series resistance100 Ω per channel branchDoes not include driver or switch resistance
Startup stateOutputs disabled; signal paths disconnectedHardware pull-ups; enable after rail settling
External drive on outputsNo sustained overvoltage ratingOutputs are not general-purpose protected inputs
Pattern vector clock100 MHz / N; 10 ns stepsDriver reports the achieved rate
Patterns page buffer4,096 vectorsLoop or one-shot; longer recipes may use a slower clock
Long-pattern memoryUp to 268 million vectors, memory-split dependentDriver/API; shared memory allocation

External trigger

8 parameters

A dedicated trigger input/output connected to the FPGA. Trigger input does not consume a capture channel. The input specifications below do not describe output drive capability.

ParameterSpecificationConditions
Trigger interfaceMCX trigger input / outputFPGA-connected interface
Connector / termination50 Ω MCX connector; high-impedance inputNo 50 Ω termination fitted
Input resistance22.68 kΩ nominalSame divider architecture as the capture inputs
Normal input range0–5 V logicCenter contact relative to MCX shell
Threshold settingIndependent; same six input modesSeparate trigger calibration
Edge selectionRising, falling or either edgeGateware-defined selection
Minimum high / low pulse10 nsAt the connector
Repetitive event rate50 MHz

Capture & processing

6 parameters

FPGA acquisition with DDR3L sample memory and USB or Ethernet transfer.

ParameterSpecificationConditions
FPGALattice ECP5 LFE5U-45F-7BG256CHardware selection
ControllerWCH CH32H417QEU6USB, Ethernet and FPGA configuration controller
External memory8 Gbit (1 GiB) DDR3L, GDP3BELM-CBPhysical memory capacity
Memory organization512M × 16; two byte lanes16-bit memory interface
Memory supply modeDDR3 at 1.5 VSelected operating mode
FPGA loadingHost-supplied gateware, loaded by the MCU over Slave SPIDefault assembly has no populated configuration flash

Connections & power

8 parameters

USB-C carries data and power. Ethernet is a separate data interface; board power comes from USB-C.

ParameterSpecificationConditions
USBUSB 3.2 Gen 1 with USB 2.0 high-speed companionHost data interface
EthernetGigabit Ethernet via RTL8211F-CGCH32H417 GMAC / RGMII interface
Internal MCU–FPGA data bus16 physical UHSIF data lines, 1.8 VMCU is the bus master
Power inputUSB Type-C, nominal 5 VSink / UFP only
Full-operation supplySource must advertise 3 A at 5 VType-C current advertisement
Default / 1.5 A sourceController enumeration onlyA 5 V / 3 A source is required for full operation
Higher-voltage USB PDNot supportedNo contract above 5 V
Steady-state input current≤2.40 AMaximum steady-state input current

Software & operating limits

6 parameters

Host-side protocol analysis and instrument hardware triggering have separate capabilities.

ParameterSpecificationConditions
Host protocol analysisCAN / ISO CAN FD, USART, SPI, I²C, LIN, 1-Wire, Manchester, parallel and PWMShared Control Hub decoding
Advanced protocol triggersFPGA protocol triggersCAN, USART, CAN FD, LIN, FlexRay, USB PD, SENT and T1S; see the Features matrix
Negative input fault−12 V not ratedNo ±12 V protection claim
Enclosure2U module formatModular Bench format
Production test documentationPer-device reports through the customer accountPublished against the supplied equipment ID
Software accessAll features across devices; no paid unlocksOpen-source software, firmware and gateware; licence details accompany source releases

Threshold modes

6 parameters

Connector transition bands. Capture groups and the external trigger select modes independently.

Connector transition bands by logic mode.
Logic modeConnector transition bandNominal internal VREF
1.2 V CMOS0.49–0.71 V0.315 V
1.8 V CMOS0.79–1.01 V0.447 V
2.5 V CMOS1.14–1.36 V0.601 V
3.3 V CMOS1.54–1.76 V0.778 V
5 V TTL1.39–1.61 V0.711 V
5 V CMOS2.39–2.61 V1.152 V

Capture triggering & synchronisation

2 parameters

Hardware trigger support is specified separately from host protocol decoding and the dedicated external input.

ParameterSpecificationConditions
Signal trigger typesEdge, pulse width, timeout, Nth edge, pattern, delay, setup/holdFPGA hardware triggers
Trigger holdoff0–24 s in the LA signal engineSee Features for timing limits

Physical specifications & supplied equipment

1 parameters

Instrument module format.

ParameterSpecificationConditions
Module format2UModular Bench format

Platform interface

Platform specification
Shared module format, control interfaces and rack configuration.
ParameterSpecificationDetail
Module format2UModular Bench format
Rack capacity7 module positionsModular Bench format
User interfaceShared touchscreenModular Bench format
Control interfacesUSB-C / EthernetModular Bench format
Power inputUSB-CModular Bench format

Documentation

System interfaces, software features and equipment records.

Software and protocol support
Control Hub features ↗
Module interfaces
Hardware platform ↗
Per-device test reports
Your equipment ↗Account sign-in required

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