Inspect flash operations
Read command names, addresses, byte counts and data beside CS#, SCK, MOSI and MISO. Select an operation to locate its range in memory.
Control Hub bench
SPI flash analyzer
Observe communication between a controller and serial NOR flash. Reconstruct the memory contents seen in reads, programs and erases, with each address linked to the operation that set it.
Logic analyser capture with decoded transactions and saved records.
Control Hub · Emulated serial NOR flash sessionAnalysis workspace
Flash commands, readback and a reconstructed memory image, linked to the captured SPI signals.
Follow memory changes
Inspect a reconstructed memory image, with unknown and assumed content marked. A sector overview provides navigation and erase counts.
Check captured sequences
Find writes without observed write enable, writes while known busy, incomplete frames and readback disagreements. Capture gaps remain visible in the result.
Control Hub screenshots
Captured in the application. Select a view to inspect its controls and results.
Actual Control Hub screenshots using emulated instruments.
Instrument connections
A logic analyser observes CS#, SCK and MOSI. Add MISO to reconstruct read data and check readback. All lines are acquired on the same analyser.
Four-wire SPI
Bind CS#, SCK, MOSI and MISO to the target signals. The bench triggers on the falling edge of CS# and repeats acquisitions.
Without MISO
Commands and outgoing writes can still be followed. Read data and readback checks remain not measured.
Electrical connection
Match the logic inputs to the target voltage and grounding. This is passive observation: the bench does not program the target or respond as a flash device.
Feature coverage
Capture, decode and inspect bus transactions.
| Capability | Implemented software coverage |
|---|---|
| Memory reconstruction | Sparse memory image with known/unknown bits, read/program/erase origins and assumed writes. Page wrapping, bit-clearing program behavior and sector erase counts. |
| Command decoding | READ/FAST_READ, page program, sector/block/chip erase, write enable/disable, status, JEDEC ID, power-down and reset. Three- and four-byte address commands and address-mode tracking. |
| Readback checks | A mismatch against a value set in the same capture is a finding. A changed value across a capture gap is reported as changed while not observed. |
| Operation log | Filter by operation kind, follow new traffic and jump between an operation and its memory range. Repeated reads and status polls can fold into grouped rows. |
| Part selection | W25Q128 and Generic 25-series profiles. The selected profile sets memory size, page layout and supported erase sizes; it is not an automatic device-compatibility guarantee. |
| Signal inspection | Latest-capture CS#, SCK, MOSI and MISO traces with command, address, dummy and data fields. The signal window displays the first 32 SPI words of a long transaction. |
Records and exports
Keep the derived data alongside the run record.
Image load and export
Load a binary or Intel HEX file into the reconstructed image. Export binary, Intel HEX or a text hex dump. Loading an image does not write the target flash.
Unknown content
Binary export fills unknown bytes with a chosen value. Intel HEX omits unknown ranges; the text dump marks them. Exported coverage must be considered before treating a file as a complete image.
Saved runs and image lifetime
Runs retain operation rows and summaries, not the memory image. Export the image separately. It continues across runs until Reset, a part change or a hub restart.
Software access
Analysis is included in the shared software. Software, firmware and gateware are open source; no decoder licence or feature unlock is required.